This invention relates to a level sensitive latch and circuits incorporating the same. A primary circuit element of binary digital logic circuits is a level sensitive latch. A latch is used in the implementation of registers that are commonly required in digital circuits.
There is a trend of increasing the number of transistors upon a chip area of an integrated circuit. The more transistors for a given area the more complex and powerful a circuit may be. However, the more transistors for a given area the more heat which is typically generated. Heat must be dissipated and is a limiting characteristic on the operational speed of the circuit. Countering this is the desire to increase operation speed.
It is an object of this invention to provide a level sensitive latch to obviate or minimize at least one of the aforementioned problems, or at least provide the public with a useful choice.
The invention may be said to reside in a binary digital logic level sensitive latch including:
a first inverter providing an output (O1) and having at least one input signal (I1) and an activation signal (Clk) both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter and the capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal:
O1={overscore (I1+Clk)}
a second inverter providing an output (O2) and having as capacitively coupled inputs the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) and a switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of:
O2={overscore ((Clkxc3x97P)+O1)}. 